Multiplexers & De-multiplexers

-

Multiplexer

Multiplexer is a combinational logic circuit designed to switch one of several input lines to a single common output line.

2 to 1 Multiplexer

The input A of this simple 2-1 line multiplexer circuit constructed from standard NAND gates acts to control which input ( I0 or I1 ) gets passed to the output at Q.

Simulation of 2 to 1 Multiplexer



4 to 1 Multiplexer

4 to 1 Multiplexer Using NAND gates





Simulation of 4 to 1 Multiplexer





De-multiplexers

The demultiplexer is a combinational logic circuit designed to switch one common input line to one of several seperate output line.



1-to-4 Channel De-multiplexer & truth table

Simulation of 1 to 4 De-multiplexer










Comments

Post a Comment

Popular posts from this blog

Introduction to CEDAR Logic Simulator

-
Image
 Cedar Logic simulator also like Logisim simulator but in Logisim there is no time diagram. So next chapters will cover using Cedar logic simualtor. How to download & Install Cedar Logic Simulator You can simply download it from here - Download Now Installation is easy, It didn't require any additional software to download. Overview of CEDAR Logic Simulator
Read more

Flip - Flops

-
Image
The basic difference between a latch and a flip-flop is a gating or clocking mechanism. In Simple words, Flip Flop is edge-triggered and a latch is level triggered. S-R Flip Flop This simple flip-flop circuit has a set input (S) and a reset input (R). In this system, when you Set “S” as active the output “Q” would be high and “Q‘” will be low. Once the outputs are established, the wiring of the circuit is maintained until “S” or “R” go high, or power is turned off. As shown above, it is the simplest and easiest to understand. The two outputs, as shown above, are the inverse of each other. Truth Table for S-R Flip flop Simulation of S-R Flip flop J-K Flip flop The JK Flip-flop is similar to the SR Flip-flop but there is no change in state when the J and K inputs are both LOW. Truth Table for J-K Flip Flop Simulation for J-K Flip Flop
Read more

Frequency Divider & Counters

-
Image
 Frequency Divider A frequency divider can be constructed from J-K flip-flops by taking the output of one cell to the clock input of the next. The J and K inputs of each flip-flop are set to 1 to produce a toggle at each cycle of the clock input. For each two toggles of the first cell, a toggle is produced in the second cell, so its output is at half the frequency of the first. The output of the fourth cell is 1/16 the clock frequency. The same device is useful as a binary counter. Simulation of Frequency Divider Counters A counting circuit composed of memory elements, such as flip-flops and electronic gates, is the simplest form of sequential circuit available. All sequential circuits are of two types,  synchronous (clock driven)  asynchronous (event driven) In synchronous circuits, changes in the circuit state are synchronised to the normally periodic clock pulses, whereas in event driven circuits state changes are governed by events such as, for example, the occurrence of a system f
Read more